Process for the production of a MIS-type integrated circuit

ABSTRACT

A process for the production of a MIS-type integrated circuit is disclosed. In order to form an integrated circuit having reciprocally electrically insulated active components in which the gates of the components do not extend above the electrical insulations used for the reciprocal insulation of the components, the process consists of covering a semiconductor substrate (30) with a first layer (32) of insulating material, depositing on the first layer (32) of insulating material a second layer including a semiconductor or conductor material in which will be formed the gates (34a) of the active components, formulation of the field oxide (46a) of the circuit used for electrically insulating the active components from one another, production of the gates (34a) of the active components, production of the sources and drains of the components by a doping of the substrate, the doping having a reverse conductivity to that of the substrate (3), formation of insulating edges (58a) on the edges of the gates (34a) of the components, production of electrical contact holes of the circuit, and production of connections of the circuit.

The present invention relates to a process for the production of aMIS-type integrated circuit (metal-insulator semiconductor) and moreparticularly of the MOS or CMOS type. It more particularly applies inthe field of electronics and information processing to the production oflogic gates, flip-flops, read-only or read/write memories, etc.

Integrated circuits and more particularly MOS or CMOS circuits arefundamentally formed from n and/or p channel transistors, which areelectrically interconnected. In integrated circuits, there are severalconductor layers located at different levels ensuring theinterconnection of the transistors of these circuits. The formation ofthese different connection levels makes it necessary to have a veryplanar circuit structure.

The stages of the processes for the production of integrated circuitsused for obtaining relatively planar structures are generally known asplanarization stages.

Unfortunately the use of such a technology in existing integratedcircuit production processes leads to serious difficulties duringcontacting of sources and drains of the transistors forming thesecircuits. This disadvantage is illustrated by the attached FIG. 1, whichis a diagrammatic longitudinal section of part of a prior art MOSintegrated circuit.

FIG. 1 shows a MOS-type transistor 2, produced on a semiconductorsubstrate 4, particularly of monocrystalline silicon. Transistor 2 has asource 6 and a drain 8, produced by ion implantation in substrate 4, aswell as a gate 10, generally made from polycrystalline silicon,surmounting a gate oxide 12 positioned above substrate 4 between source6 and drain 8. The active zone of said transistor 2 is surmounted by aninsulating layer 14, generally made from silicon dioxide and servinginteralia to insulate gate 10 from the source 6 and drain 8 of saidtransistor. In said insulating layer 14 are formed electrical contactholes 16, 18, respectively, permitting the electrical contacting withthe transistor source 6 and drain 8.

This transistor 2 is electrically insulated from the other componentsand particularly the other transistors constituting the integratedcircuit by silicon dioxide zones 20, which are partly buried in thesubstrate and constituting what is called the field oxide of thecircuit. On said field oxide is generally produced a firstinterconnection level 22 permitting the interconnection of part of thetransistors of the integrated circuit. The oxide layer 14, in which areformed the contact holes 16 and 18 of the source and drain also permitsan electrical insulation between the first interconnection level 22 ofthe integrated circuit and the following level.

In order to ensure a good electrical insulation between the firstinterconnection level 22 and the next level, it is necessary for theinsulating layer 14 to have, between said first interconnection leveland the next level, a minimum height h, which is typically approximately0.7 μm. Bearing in mind the thickness of the field oxide 20 (close to0.5 μm) and the first interconnection line 22, said minimum height hleads to the production of the electrical contact holes such as 16 and18 with a relatively large depth H, which is typically approximately 1.4μm.

The production of relatively deep electrical contact holes causesnumerous problems with regard to the contacting of sources and drains,such as the appearance of cracks or breaks in the conductive layerdeposited within the contact holes serving to interconnect the sourcesand/or drains of the transistors and as a result the transistors andintegrated circuits produced are defective.

As has been stated hereinbefore, the surface of the integrated circuitsmust be made as planar as possible during each stage of theirproduction, so as to facilitate the production of the differentconnections of said circuits.

However, one of the factors prejudicial to the planarity of theintegrated circuits is the overlapping of the field oxide thereof by thegate electrode of the components or transistors of said circuits. Thisis illustrated by FIG. 2 showing, in cross-section, part of theintegrated circuit of FIG. 1. In the latter, the overlap zones of thegate 10 of the MOS transistor on field oxide 20 carry the reference 26.

Apart from these problems and bearing in mind the evolution ofintegrated circuits and their increasing significance for producingcircuits in electronics and/or information processing, increasingefforts are being made to reproduce the dimensions of the componentsforming them and particularly transistors, i.e., for increasing theintegration density of said circuits.

However, one of the factors limiting the integration density ofintegrated circuits is the production of the electrical contact holessuch as 16 and 18 in the insulating material layer 14 (FIG. 1). Thus,the correct positioning of these contact holes facing the source region6 and drain region 8 formed in said substrate 4 makes it necessary toprovide insulation protectors such as 24 in insulating layer 14.

The present invention is directed at the production of an integratedcircuit, particularly of the MOS or CMOS type, which makes it possibleto solve the aforementioned problems. It more particularly permits easycontacting of the sources and drains of the transistors of theintegrated circuit, while making it possible to produce integratedcircuits having a substantially planar structure, while significantlyincreasing the integration density of these circuits.

The present invention aims at producing an integrated circuit havingactive components and particularly MOS transistors, which areelectrically insulated from one another and whose gates do not extendabove the electrical insulations used for insulating said componentsfrom one another. This makes it possible to improve the planarity of theintegrated circuits and consequently facilitate the production ofconnections between the different components of said circuits.

More specifically, the present invention relates to a first process forthe production, on a semiconductor substrate, of an integrated circuithaving reciprocally electrically insulated components in which the gatesof said components do not extend above the electrical insulations usedfor the reciprocal insulation of said components, said process beingcharacterized in that it comprises, in sequence, the following stages:

(a) covering a semiconductor substrate with a layer of a firstinsulating material,

(b) deposition on the layer of the first material a layer of a secondsemiconductor or conductor material in which will be formed the gates ofthe active components,

(c) formation of the field oxide of the circuit used for electricallyinsulating the active components from one another,

(d) production of the gates of the active components,

(e) production of the sources and drains of the components by a dopingof the substrate, said doping having a reverse conductivity to that ofthe substrate,

(f) formation of insulating edges on the edges of the gates of thecomponents, and

(g) production of electrical contacts and connections of the circuit.

As a result of the sequence of stages, this first process makes itpossible to increase the integration density of the integrated circuitsand facilitate the production of the different connections of thesecircuits. Moreover, the different stages of this process are notcritical and are easily and reproducibly produced, which is not alwaysthe case in the prior art processes. This process can consequently beadvantageously used for industrial mass production of integratedcircuits and particularly MOS or CMOS circuits.

According to a preferred embodiment of the first process of theinvention, the field oxide of the integrated circuit, i.e., theinsulation zones is produced by performing, in sequence, the followingstages:

(1) definition of the regions of the substrate in which will be producedthe active components with the aid of a first positive mask,

(2) elimination of the regions of the different material layerssurmounting the substrate and free from the first mask, so as to exposecertain regions of the substrate,

(3) preliminary doping the substrate in the exposed regions thereof,said preliminary doping having the same type of conductivity as that ofthe substrate,

(4) eliminating the first mask,

(5) deposition of a layer of a third insulating material on the completestructure obtained, and

(6) etching the third material layer, so as to expose the etchedmaterial layer located directly below the third material layer.

The term positive mask is understood to mean a mask defining the regionscovering it. Negative mask means a mask defining the regions notcovering it.

The production of the field oxide of the integrated circuit, asdescribed hereinbefore, greatly contributes to increasing theintegration density of said circuit. Moreover, compared with theconventional field oxide production process called LOCOS, it makes itpossible to obviate carrying out an irksome, long heat treatment stage,leading to a diffusion into the substrate of the implanted ionsnecessary for the doping beneath the field oxide.

The present invention also relates to a second process for theproduction of an integrated circuit, in which the gates of thecomponents do not extend above the electrical insulation used forreciprocally insulating the various components. This second process ischaracterized in that it comprises, in sequence, the following stages:

(α) producing the field oxide of the circuit used for electricallyinsulating the active components from one another,

(β) covering the substrate with a layer of a first insulating material,

(γ) depositing on the complete structure a layer of a semiconductor orconductor material in which will be formed the gates of the activecomponents,

(δ) etching the layer of second material so as to expose the fieldoxide,

(ε) producing the gates of the active components,

(ζ) producing the sources and drains of the components by a doping ofthe substrate, said doping having a reverse conductivity to that of thesubstrate,

(η) producing insulating edges on the edges of the gates of thecomponents, and

(θ) producing electrical contacts and connections of the circuit.

Like the first, this second process makes it possible to significantlyincrease the integration density of the integrated circuits and tofacilitate the production of the different connections of said circuits.

According to a preferred embodiment of the second process of theinvention, the field oxide of the integrated circuit is produced bycarrying out, in sequence, the following stages:

carrying out a preliminary doping of the substrate having a conductivityof the same type as that of the substrate,

deposition of a layer of a third insulating material on the completesemiconductor substrate,

definition of the regions of the substrate in which will be formed theactive components with the aid of a first negative mask,

elimination of the regions of the layer of the third material free fromsaid first mask, and

elimination of the said first negative mask.

Other features and advantages of the invention can be better gatheredfrom the following illustrative and nonlimitative description withreference to the attached drawings, wherein show:

FIG. 1 Already described, diagrammatically and in longitudinal sectionan integrated circuit according to the prior art.

FIG. 2 Already described, diagrammatically and in cross-section part ofthe integrated circuit of FIG. 1.

FIGS. 3 to 17 Diagrammatically and in longitudinal section the variousstages of the first process for the production of an integrated circuitaccording to the invention, FIGS. 7a and 13a illustrating variants ofsaid first process.

FIGS. 18 to 20 Diagrammatically and in longitudinal section part of thedifferent stages of the second integrated circuit production processaccording to the invention.

FIG. 21 Diagrammatically and in longitudinal section part of anintegrated circuit according to the invention.

The following description relates to the production of a MOS integratedcircuit having a single N channel transistor, for the purpose ofsimplifying said description. However, the invention has a much moregeneral scope, because it applies to any MIS integrated circuit producedon a semiconductor substrate, the latter being a solid substrate or asemiconductor layer surmounting an insulating support.

The transposition of the following description to CMOS technology,essentially involving the supplementary operation of doping and inparticular ion implantation is obvious to the expert. The same applieswith regards to the production of P channel transistors.

Moreover, certain stages of the process according to the invention, suchas cleaning stages, will not be described hereinafter, because they arewell known to the expert.

With reference to FIGS. 3 to 17, a description will be given of a firstprocess for the production of an integrated circuit according to theinvention. This first process firstly consists, as shown in FIG. 3, ofcovering a semiconductor substrate 30, particularly of p monocrystallinesilicon, with a first layer 32 of an insulating material, which ispreferably of silicon dioxide. The first layer 32 in particular has athickness of 0.025 μm and can be obtained by thermal oxidation of thesilicon substrate 30 at a temperature close to 900° C. This silicondioxide layer 32 will subsequently form the gate oxide of the N channelMOS transistor to be produced.

Through said silicon dioxide layer 32 is effected a doping of thesubstrate 30 used for defining the doping beneath the transistorchannel, said doping having a conductivity of the same type as that ofsubstrate 30. This doping can be obtained by ion implantation andparticularly by implanting boron ions when the substrate is of the ptype. This involves a first implantation at a dose of 10¹² atm/cm² withan energy of 50 keV and a second implantation at a dose of 4·10¹¹atm/cm² with an energy of 140 keV.

The following stage of the first process consists of depositing on thefirst layer 32 of insulating material, a second layer 34 of a conductoror semiconductor material, in which will subsequently be formed the gateof the N channel MOS transistor. Preferably, the second layer 34 is madefrom polycrystalline silicon, which may or may not be doped withphosphorus, molybdenum, tungsten, tantalum or titanium silicides, or arefractory metal such as molybdenum, tantalum, titanium and tungsten.The deposition of said second layer 34 can be obtained by a chemicalvapour phase deposition process (CVD or LPCVD) or by magnetronsputtering.

In a first variant of the first process, shown in the right-hand part ofFIG. 3, there is a single conductor or semiconductor layer 34 and it hasa thickness of approximately 1.2 μm.

In another variant, shown in the left-hand part of FIG. 3, saidconductor layer 34 only has a thickness of approximately 0.3 μm and issuccessively covered with an insulating layer 36, made from aninsulating material, preferably silicon dioxide, and a temporary layer38 made from a conductor or semiconductor material which does not becomepart of the finished product

Insulating layer 36, e.g., having a thickness of 0.07 μm, can beobtained by thermal oxidation of the second layer 34, when the latter ismade from polycrystalline silicon or silicides, at a temperature ofapproximately 900° C. In other cases, layer 36 can be obtained bydeposition and particularly by a chemical vapor phase deposition process(CVD or LPCVD). Layer 36 will subsequently serve as the etching barrierlayer.

The semiconductor or conductor material temporary layer 38 surmountingthe insulating layer 36 can be made, like the second layer 34,particularly from polycrystalline silicon, silicides, molybdenum,tantalum, titanium and tungsten. Temporary layer 38 which has athickness of 0.6 μm can be obtained by a chemical vapor phase depositionprocess (CVD or LPCVD). Temporary layer 38 mainly has a topologyfunction, rather than a physical or electrical function.

The following stages of the first process consist of producing theintegrated circuit insulations, mainly constituted by the field oxide ofsaid circuit. Firstly and both in the case of a thick conductive secondlayer 34 and a stack of layers 34, 36 and 38, using conventionalphotolithography processes, a resin or positive mask 40 is produced,which serves to define the region of substrate 30 in which will beformed the N channel transistor. This mask is positive, because it masksthe region of substrate 30 in which the transistor will be formed. Then,as shown in FIG. 4, the regions of the different layers of the materialsurmounting the substrate 30 are eliminated, i.e., layers 32 and 34(first variant on the right-hand side of FIG. 4) or layers 32, 34, 36and 38 (second variant on the left-hand side of FIG. 4), which are freefrom mask 40 up to the exposure of the regions of substrate 30 notcovered by said mask.

This elimination can be carried out by successive anisotropic etchingprocesses and particularly reactive ion etching processes of thedifferent layers of material surmounting the semiconductor substrate.The insulating layers, particularly of silicon dioxide 32, 36 can beetched with trifluoromethane (CHF₃) and the conductive layers 34, 38,when the latter are made from polycrystalline silicon or silicides, byusing sulphur hexafluoride (SF₆).

Through using different etching agents as a function of whether thelayers are insulating (layers 32 and 36) or conductive or semiconductive(layers 34 and 38) makes it possible to use the layer positioned belowthat which is etched as the etching barrier layer, which makes itpossible to compensate the thickness inhomogeneities of these differentlayers.

Optionally and as shown in FIG. 4, there is then an etching of theexposed substrate regions over a thickness e, using positive mask 40 asthe mask for said etching process. This etching of the substrate willsubsequently make it possible to obtain a partly buried field oxide, asin conventional oxide production processes. The thickness of etching eis, e.g., approximately 0.4 μm. The etching of substrate 30 or morecorrectly its exposed regions is preferably carried out anisotropically,e.g., using reactive ion etching with sulphur hexafluoride as theetching agent in the case of a silicon substrate.

The following stage in the production of the field oxide according tothe invention consists, still using the same resin positive mask 40,carrying out a preliminary doping of substrate 30 or the exposed regionsthereof, said preliminary doping having a conductivity of the same typeas that of the substrate. This doping can, e.g., be carried out by ionimplantation, while more particularly implanting boron ions, in the caseof a type p substrate at an energy of 80 keV and a dose of 10¹² atm/cm².This doping makes it possible to obtain two lateral regions 42 and 44,particularly of type p⁺. Following said doping, the resin positive mask40 is eliminated, e.g., by etching with an oxygen plasma.

As shown in FIG. 5, this is followed by the deposition on the completestructure of a third layer 46 of an insulating material, e.g., formedfrom optionally phosphorus-doped silicon dioxide. This insulating thirdlayer 46, e.g., has a thickness of 1.5 μm. It can be obtained by a lowpressure chemical vapor phase deposition process (LPCVD) and preferablywith plasma assistance (PECVD). This insulating layer 46 can thenadvantageously undergo a heat treatment, e.g., at a temperature of 1050°C. for 10 mn, so as to compact layer 46.

The final stage for obtaining the field oxide of the integrated circuitaccording to the invention consists of etching the more particularlysilicon dioxide third layer 46, so as to expose the etched materiallayer directly below third layer 46.

In the variant shown in the left-hand part of FIG. 5, the etching of theinsulating third layer 46 will make it possible to expose the conductoror semiconductor temporary layer 38 and in the variant shown in theright-hand part thereof, the etching of layer 46 will make it possibleto expose the thick conductor or semiconductor second layer 34.

Insulating third layer 46 is advantageously etched (in accordance withplanarization technology) by depositing in per se known manner on saidthird layer, a fourth layer 48 of a planation material obliterating therelief of third layer 46. Planation fourth layer 48 is preferably madefrom resin of the type widely used in photolithography. The depositionof resin fourth layer 48, which more particularly has a thickness of 1.5μm, can be followed by a heat treatment, e.g., heating at a temperatureof approximately 200° C. for 30 minutes, so as to obtain a goodspreading of the resin fourth layer 48 and consequently a good planarsurface.

This is followed by the simultaneous etching of resin fourth layer 48and insulating layer 46, which is more particularly of silicon dioxide,at identical etching speeds for the resin and the oxide up to the totalelimination of the region of layer 46 (cf. FIG. 6) surmounting eitherthe etched conductor or semiconductor temporary layer 38 (to the left inthe drawing) or the etched conductor or semiconductor layer 34 (to theright in the drawing). This etching which leads to the obtaining of afield oxide 46a with a perfectly planar surface is preferably carriedout anisotropically, e.g. using a reactive ion etching process with theetching agent being formed by a mixture of trifluoromethane ortetrafluoromethane (CHF₃ or CF₄) and oxygen; the fluorine-containingcompounds being used for etching the silicon dioxide and the oxygen foretching the resin.

The following stages of the first production process for an integratedcircuit according to the invention deal with the production of gates ofactive components of said circuit and in the present case the gate ofthe N channel MOS transistor.

As shown in FIG. 6, the production of the gate of said transistorfirstly consists of defining the dimensions of the gate and theelectrical connections of said gate with the aid of a negative mask 50,referred to as the gate negative mask more particularly made from resinplaced about the structure. The width of the opening 52 of the negativemask exactly corresponds to that of the gate of the transistor to beproduced. Moreover, opening 52 of mask 50 projects beyond the fieldoxide 46a, so as to be able to effect a connection of said gate. This isshown in FIG. 21, which in cross-section, shows part of an integratedcircuit according to the invention. The projection of the conductivelayers 62, 64 over the field oxide 46a corresponds to the projection ofopening 52 over the field oxide and consequently to the connection ofthe gate.

In a first variant, shown in the right-hand part of FIG. 7, using mask50 a first etching of the conductor or semiconductor layer 34 is carriedout over a height of approximately 0.6 μm. This etching can be carriedout anisotropically, e.g., using a reactive ion etching process withsulphur hexafluoride as the etching medium, when said layer is made frompolycrystalline silicon. The end of etching can be checked by any knownmeans.

In a second variant, shown in the left-hand part of FIG. 7 andcorresponding to the use of a thinner conductor or semiconductor layer34 successively covered with an insulating layer 36 and a conductor orsemiconductor temporary layer 38, using gate negative mask 50, temporarylayer 38 is etched so as to eliminate therefrom the regions not coveredby mask 50 and expose the underlying regions of insulating layer 36.Said etching can be carried out by reactive ion etching using sulphurhexafluoride as the etching medium for a polycrystalline silicon layer38.

This mask can optionally be used for defining, besides those of the gateand the gate connections, the dimensions of the short distanceconnections to be produced between the activity zones, i.e., sourceand/or drain of the transistor of the integrated circuit with theactivity zones, i.e., a source and/or drain or another transistor of thesame circuit. For example, mask 50a as shown in FIG. 7a, can be providedwith an opening 53, whose dimensions correspond to those of a connectionto be produced, e.g., a connection of the transistor drain. Opening 53projects slightly above the region of the transistor to be produced inorder to take account of positioning tolerances between mask 50a andmask 40 (FIG. 3).

After etching conductor or semiconductor layer 34 (right-hand part ofthe drawing) or semiconductor or conductor temporary layer 38 (left-handpart of the drawing), etching takes place in field oxide 46a using mask50 or 50a over a height of approximately 0.6 μm. This etching can becarried out anisotropically by a reactive ion etching process usingtrifluoromethane as the etching agent.

After eliminating mask 50 or 50a, which is particularly made from resinusing an oxygen plasma, the structure can optionally be covered, asshown in FIG. 8, with a layer 54, called the edge insulating materiallayer made of an insulating material, e.g., silicon dioxide. In the caseof a layer 34 (right-hand part of the drawing) or a temporary layer 38(left-hand part of the drawing) made from polycrystalline silicon orsilicide, the edge insulating material layer 54 can be obtained bythermal oxidation at a temperature of approximately 900° C. of thesilicon or silicide. The edge insulating material layer 54 has athickness of approximately 0.1 μm.

This is followed by an etching of the edge insulating material layer 54so that, as shown in FIG. 9, all that is left thereof are the verticalstrips 54a on the etched edges of the semiconductor or conductor layer34 or 38, as a function of the variant used, the horizontal regions ofsaid layer being eliminated. Moreover, said etching of the edgeinsulating material layer 54 makes it possible to eliminate the exposedregions of insulating layer 36 during the etching of temporary layer 38by using the mask 50 or 50a defining the dimensions of the transistorgate, in the case of the process variant using the two layers 36 and 38.Said etching can be carried out anisotropically by a reactive ionetching process using trifluoromethane as the etching medium in the caseof a silicon dioxide edge layer material 54.

The production of the transistor gate continues by depositing on thecomplete structure a planation material layer 56, called theplanation/gate mask layer used for obliterating the structure relief.Layer 56 is preferably of polyimide. Following the deposition of saidpolyimide layer, the latter can undergo a heat treatment, such asheating at a temperature of approximately 400° C. for 30 minutes, so asto obtain a good spreading of layer 56, as well as a planar surface anda good hardening (crosslinking) of the polyimide.

Finally, the planation/gate mask layer 56, preferably of polyimide, isetched so as to only leave those parts filling the hollowed out regionsof the structure so that, following the etching of layer 56, a perfectlyplanar structure is obtained, in the manner shown in FIG. 10.

The hollowed out parts correspond to the etched region of layer 34 or 38and optionally that of field oxide 46a (FIG. 7a), on defining the shortdistance connections of the integrated circuit at the same time as thoseof the transistor gate. When the planation/gate mask layer 56 is ofpolyimide, the etching thereof can be effected by reactive ion etchingusing oxygen as the etching medium.

In the case of a thick conductor or semiconductor layer 34 this isfollowed, in the manner shown in the right-hand part of FIG. 11, by anetching of said layer, so as to eliminate the regions thereof notcovered with the remaining planation/gate material layer 56. Thisetching is carried out so as to expose the underlying first layer 32 ofinsulating material. It can be carried out by an anisotropic etchingprocess and particularly by a reactive ion etching process using sulphurhexafluoride as the etching medium, when layer 34 is of polycrystallinesilicon.

In the variant of a thin conductor or semiconductor layer 34 coveredwith an insulating layer 36 and a conductor or semiconductor layer 38,in the manner shown in the left-hand part of FIG. 11, what is left oftemporary layer 38 is eliminated, followed by the etching of insulatinglayer 36 and the conductor or semiconductor layer 34 until the firstlayer 32 of insulating material is exposed, etched planation/gate masklayer 56 serving as a mask for said etching process. These etchingprocesses are performed using the remainder of planation/gate mask layer56 as a mask.

Preferably, these etching processes are carried out anisotropically byreactive ion etching using sulphur hexafluoride as the etching agent forconductive layers 38, 34 made from polycrystalline silicon andtetrafluoromethane for insulating layer 36 made from silicon dioxide. Ashereinbefore, the change of the etching product for the etchingprocesses makes it possible to use the layer below that being etched asthe etching barrier layer, so that the inhomogeneities of the differentlayers are compensated.

The use of an insulating layer 36 placed between two conductor orsemiconductor layers 34, 38 makes it possible to improve and facilitatethe different etching processes of said layers compared with the use ofa single thick layer 34 and consequently facilitates the production ofthe transistor gate 34a.

The following stage of the first process for the production of anintegrated circuit according to the invention consists of producing thesource and drain of the N channel MOS transistor of said circuit. Source57 and drain 59 are obtained by doping substrate 30 having aconductivity of the reverse type as compared with that of the substrate.For example, in the case of a type p silicon substrate, the doping canbe effected by ion implantation by implanting arsenic ions, particularlyat a dose of 5.10¹⁵ atm/cm² with an energy of 100 keV. This ionimplantation is carried out through the first layer 32 of insulatingmaterial which is particularly of silicon dioxide and forms the gateoxide.

The following stages of the first production process according to theinvention relate to producing insulating edges on the edges of the gate34a of the MOS transistor of said circuit.

For this purpose, layer 58 called the insulating strip material layer ofan insulating material, particularly of silicon dioxide is deposited onthe complete structure. This insulating strip material layer 58, which,e.g., has a thickness of 0.3 μm, is isotropically deposited, e.g., bymeans of a plasma-assisted low pressure vapor phase chemical depositionprocess (PECVD) at a low temperature of e.g., close to 350° C.

In the manner shown in FIG. 12, this is followed by the etching of saidinsulating strip material layer 58, so as to only leave the insulatingstrips 58a on the etched edges of the structure. The latter are inparticular the edges of gate 34a, the insulating edges 54a and the edgesof the field oxide 46a. The insulating strips 58a can advantageously beproduced by anisotropically etching layer 58, more particularly using areactive ion etching process. Thus, this type of etching makes itpossible to obtain insulating strips 58a, whereof the width is definedby the thickness of the isotropically deposited insulating stripmaterial layer 58. In particular, a 0.3 μm thick layer 58 makes itpossible to obtain 0.3 μm wide insulating strips 58a. In the case of asilicon dioxide layer 58, the latter can be etched by usingtrifluoromethane as the etching agent.

The etching of insulating strip material layer 58 also makes it possibleto eliminate those regions of the first layer 32 of insulating materialpositioned above source 57 and drain 59 of the transistor, as shown inFIG. 12.

The aforementioned formation of insulating strips 54a surmounting thetransistor gate 34a makes it possible to improve the behaviour of theremainder of the more particularly resin planation/gate mask layer 56and consequently the profile of insulating strips 58a.

As shown in FIG. 13, the following stage of the first process accordingto the invention consists of producing on the complete structure anegative mask 60 called contact holes negative mask, particularly ofresin, representing the image of the short distance connections betweenthe activity zones, i.e., source 57 and/or drain 59 of the integratedcircuit transistor with the activity zones, i.e., a source and/or drainof another transistor of the same integrated circuit, in the case wherethe dimensions of the connections to be produced were not defined at thesame time as those of the transistor gate and those of the connectionsof said gate (FIG. 7a). In other words, mask 60 makes it possible todefine the dimensions of these connections. In the case shown in FIG.13, mask 60 makes it possible, through its opening 61 projecting abovedrain 59, to define the dimensions of a connection of said drain to beproduced.

Using mask 60, this is followed (FIG. 14) by the etching of field oxide46a over a height of 0.6 μm, as well as an etching of insulating strips58a not covered by mask 60 and in this particular case only theinsulating strip located in the opening 61. The insulating strips areetched at roughly the same speed as the field oxide 46a. Following saidetching, all that is left is a portion A of strip 58a located in theopening 61 of mask 60, whose height is equal to that of the leveldifference between drain 59 and the bottom of the etching of field oxide46a. The etching of insulating layer 46a, in which is formed the fieldoxide, and the etching of the silicon dioxide insulating strips 58apreferably take place anisotropically using a reactive ion etchingprocess, with trifluoromethane as the etching agent.

When the dimensions of the connections of the short distance transistorof the sources and drains to be produced have been defined at the sametime as those of the gate of the latter and the connections of said gate(FIG. 7a), use is then made of a more particularly resin negative mask60a also called a contact holes negative mask, as shown in FIG. 13a,then representing solely the image of the electrical contacts to beproduced of the transistor activity zones, i.e., source 57 and/or drain59. Using said mask 60a defining the dimensions of these contacts and inthe present case only those of the contact of drain 59, the insulatingstrips 58a on either side of the connections to be produced areeliminated and in the particular case only the strips 58a located on theside of drain 59, whilst retaining those located on either side of thetransistor gate 34a. This elimination can, e.g., be carried out bychemical etching, e.g., using hydrofluoric acid when the insulatingstrips are made from silicon dioxide.

In FIG. 13a, element B corresponds to a residue of layer 34 resultingfrom the etching of part of said layer during the etching of field oxide46a (FIG. 7a).

The first stage of the first process consists, as shown in FIG. 14, ofeliminating mask 60 or mask 60a, particularly by using an oxygen plasmaand then eliminating the remainder of the more particularly resinplanation/gate mask layer 56 in the same stage.

Following the elimination of mask 60 or 60a and the remainder ofplanation/gate mask layer 56, a further doping is advantageously carriedout in the transistor source 57 and drain 59, said doping having aconductivity of the reverse type compared with that of substrate 30.This doping, which is more particularly carried out by ion implantationmakes it possible to obtain at the transistor gate 34a a doublesource-drain junction, which makes it possible to reduce the electricfield between the transistor drain and gate. In the case of a type psubstrate, said doping can be carried out by implanting arsenic ionswith an energy of 130 keV and a dose of 5.10¹⁵ atm/cm².

The following stage of the process consists of annealing the completestructure obtained, so as to make electrically active the implantedions, particularly during the production of the transistor source 57 anddrain 59, whilst also rearranging the crystal lattice of the substrate,which was disturbed during the implantation. Annealing can be carriedout in an oven at a temperature of approximately 900° C. forapproximately 30 minutes.

The following stage of the process consists of eliminating the silicondioxide, which may have formed during the elimination of mask 60 and theremainder of planation/gate mask layer 56, bearing in mind the etchingagent used, i.e., the oxygen plasma when mask 60 and layer 56 are madefrom resin. This elimination can be obtained by a reactive ion etchingprocess using a mixture of trifluoromethane and oxygen with a 5% byvolume oxygen concentration.

The following stages of the first process relate to the formation of theelectrical contacts and short distance connections of the integratedcircuit, i.e. the connections between the sources and/or drains of thecircuit transistors.

In the manner shown in FIG. 15, there is firstly a deposition of a layer62 of a conductor or semiconductor material (eleventh material),followed optionally by the deposition of a layer 64 of another conductoror semiconductor material. Layer 62 acts as a diffusion barrier forlayer 64, so as to ensure that the latter does not react with substrate30 or gate 34a. Layer 62, e.g., has a thickness of 0.1 μm and layer 64 athickness of 0.3 μm. These layers can be made from any materialgenerally used in the production of integrated circuits. In particularthey can be made from silicide or a refractory metal (molybdenum,platinum, tantalum, tungsten and titanium), but can also be made fromother less usual materials such as copper, silver, aluminum, etc.

Preferably, layer 62 is made from a titanium-tungsten alloy and layer 64from aluminum. The deposition of layer 62 and also layer 64 can becarried out by a magnetron sputtering process.

Layers 62 and 64 will also be used for producing the shunt resistor ofthe transistor gate 34a. Through producing layers 62, 64 respectively ofa titanium-tungsten alloy and aluminum, it is possible to obtain a tentimes lower shunt resistance than in the prior art processes, whichmakes it possible to increase the operating speed of the transistor andtherefore the integrated circuit.

This is followed by the deposition of planation/contact covering layer66 on conductor or semiconductor layer 64, so that the relief of thelatter is obliterated. Preferably, planation/contact covering layer 66is made from resin, like those currently used in photolithography.Following its deposition, resin layer 66 can undergo a heat treatment,e.g., baking at approximately 200° C., so as to obtain a good spreadthereof and consequently a planar surface.

This is followed by the etching of planation/contact covering layer 66,so as to only retain the hollowed out portions of the relief. Followingthe etching of layer 66, the resulting structure then has a planarsurface, as shown in FIG. 15. Said etching is preferably carried out bya reactive ion etching process using oxygen as the etching agent whenlayer 66 is made from resin.

The following stage of the first process consists, as shown in FIG. 16,eliminating the regions of layer 64 and then those of layer 62 notcovered with the remainder of planation/contact covering layer 66. Thiselimination can be carried out by anisotropic etching, such as reactiveion etching using carbon tetrafluoride as the etching agent for analuminum layer 64 and sulphur hexafluoride for a titanium-tungsten alloylayer 62. This is followed by the elimination of the remainder of layer66, e.g., using an oxygen plasma. The structure obtained is shown inFIG. 17.

The preceding stages, relating to the definition and production ofelectrical contacts and short distance connections of the integratedcircuit, permit an auto-positioning or self-alignment of the transistorsource and drain contacts with respect to the transistor gate. Moreover,they make it possible to considerably increase the integration densityof integrated circuits compared with the prior art, by eliminating themore particularly silicon dioxide insulating material layer in which areformed the electrical contact holes of the sources, drains and gates ofthe components by etching said layer (layer 14 in FIG. 1).

The following stages of the first process consist of producing the longdistance connections between the different components of the integratedcircuit. These connections are produced in a conventional manner, asshown in FIG. 17, by depositing an insulating layer 68, particularly ofsilicon dioxide, by forming the different electric contact holes in saidinsulating layer, by depositing a conductive layer 70, particularly ofaluminum on the complete structure and by etching said layer with anappropriate mask so as to form the different connections.

The electric contact holes are preferably produced above the field oxideregions 46a, so as to have a single hole depth.

In view of the quasi-planarity of the structure obtained by theintegrated circuit production process according to the invention (FIG.17), the production of these long distance connections is greatlyfacilitated compared with the prior art processes.

FIGS. 18 to 20 diagrammatically show in longitudinal section thedifferent stages of a second process for producing an integrated circuitaccording to the invention. As hereinbefore, the following descriptionrelates to the production of a MOS integrated circuit having a single Nchannel transistor, so as to simplify the description.

As the material layers have the same function as those described for thefirst production process, they carry the same references to which 100has been added.

The first stage of this second process, illustrated by FIG. 18, consistsof carrying out, in a semiconductor substrate 130, particularly of typep monocrystalline silicon, a preliminary doping with a conductivity ofthe same type as that of the substrate. This preliminary doping makes itpossible to simultaneously define the doping beneath the transistorchannel, as well as the doping of the field oxide of the integratedcircuit to be produced. Such a doping system is described in an articlein IEEE Transaction on Electron Devices, vol. ED 29, No. 4, April 1982,by K. L. WANG et al, entitled "Direct Moat Isolation for VLSI".

Preferably, this preliminary doping is carried out by ion implantationby implanting boron ions, in the case of a p substrate, and a dose of5.3·10¹¹ atm/cm² with an energy of 80 keV, followed by anotherimplantation at a dose of 3.2·10¹¹ atm/cm² with an energy of 150 keV.

The following stage of this second process consists of covering thesemiconductor substrate 130 with a layer of insulating material 146,preferably silicon dioxide, in which will subsequently be formed thefield oxide of the integrated circuit. Layer 146 can be obtained bydeposition and particularly by a low pressure vapor phase chemicaldeposition process (LPCVD) preferably with plasma assistance (PECVD).Insulating layer 146, e.g., has a thickness of 1 μm.

Using conventional photolithography processes, a more particularly resinnegative mask 140 is formed on insulating layer 146. Negative mask 140makes it possible to define the substrate region in which willsubsequently be produced the N channel transistor of the integratedcircuit.

As shown in FIG. 19, this is followed by the etching of the insulatinglayer 146, so as to eliminate therefrom those regions not covered withmask 140. This etching can be carried out anisotropically andparticularly by a reactive ion etching process using trifluoromethane asthe etching agent when layer 146 is made from silicon dioxide. The thusformed field oxide carries reference 146a. The following stage of thesecond process consists of eliminating the resin mask 140, particularlyusing an oxygen plasma.

This is followed by the covering of the exposed substrate regions withan insulating material and more particularly silicon dioxide layer 132.Layer 132 can, e.g., be obtained by thermal oxidation of the substrateat a temperature of approximately 900° C. Layer 132 has a thickness of0.025 μm. The oxide layer 132 will subsequently form the transistor gateoxide.

A layer 134 of a conductor or semiconductor material is then depositedon the complete structure and the transistor gate will be subsequentlyformed therein. Layer 134 is deposited by a vapor phase chemicaldeposition process. Layer 134, e.g., has a thickness of 1.2 μm and canbe made with phosphorus-doped or non-phosphorus-doped polycrystallinesilicon, silicide or a refractory metal, such as molybdenum, tantalum,titanium and tungsten.

The following stage of the second process consists of etching layer 134,so as to expose the field oxide 146a. As shown in FIG. 19, this can becarried out by depositing on the conductor or semiconductor layer 134, alayer 149 of a planation material for obliterating the relief of layer134. Layer 149 is preferably made from resin, such as that currentlyused in photolithography. Following its deposition, layer 149 canundergo a heat treatment permitting a good spreading thereof.

This is followed by the simultaneous etching of conductor orsemiconductor layer 134 and, planation layer 149 at identical etchingspeeds for the two layers. In the case of a polycrystalline siliconlayer 134 and a resin layer 149, said etching can be carried out byreactive ion etching using as the etching agent sulphur hexafluoride andoxygen, the sulphur hexafluoride being used to etch the polycrystallinesilicon and the oxygen to etch the resin.

The structure obtained after etching the conductor or semiconductorlayer 134 is shown in FIG. 20.

The following stages of the second process consist of producing, ashereinbefore, the transistor gate (FIGS. 6 to 11), the transistor sourceand drain (FIG. 12), as well as the different contacts and electricalconnections of said circuit (FIGS. 13 to 17).

It should be noted that this second process is a little more criticalthan the first process, particularly due to the absence of insulatingtemporary layer 36, serving as a barrier layer for the etching processesof the conductor or semiconductor layer 38 and the need to carry out thedoping of the field oxide and the transistor channel at the same timeand in an identical manner.

The two processes for producing an integrated circuit describedhereinbefore involves several stages linked up in very different waysfrom those of the presently known processes. These two processes make itpossible to obtain an integrated circuit, like that shown incross-section in FIG. 21.

This integrated circuit has a gate 34a surrounded by the field oxide 46aof the integrated circuit and not extending over said field oxide, i.e.,above the electrical insulations of the circuit. The layer 32 forms, ashereinbefore, the gate oxide and layers 62 and 64 form the conductinglines defining the shunt resistance of the gate, as well as theconnections of gate 34a. Preferably, layer 62 is made from atitanium-tungsten alloy and layer 64 from aluminum, which gives theshunt resistance a ten times lower value than in prior art, bearing inmind the good electrical properties of these materials.

The fact that gate 34a does not extend above the integrated circuitfield oxide 46a means that the circuit has a quasi-planar structure,which significantly facilitates the production of the connections ofsaid transistor to the other components of the integrated circuit.

The embodiments of the processes according to the invention describedhereinbefore have been given in exemplified manner and certainmodifications to the different stages of these processes can be madewithout passing beyond the scope of the invention.

In particular, the elimination of the more particularly resinplanation/gate mask layer 56 could be carried out prior to thedeposition of insulating strip material layer 58 for producing theetched edges 58a (FIGS. 11 and 12). In the same way, the etching of thefield oxide 46a (FIG. 7a) during the definition of the dimensions of thetransistor connections at the same time as those of the transistor gatecan be carried out prior to etching the conductive layer 38 or 34.

Furthermore, the annealing used for making the implanted ionselectrically active in order to define the source 57 and drain 59 of thetransistor can be carried out just after said implantation andparticularly when said implantation is not to be followed by otherimplantations.

Moreover, the different material layers used in the processes accordingto the invention can be obtained in a manner other than that described.In particular, for insulating layers above a conductor or semiconductorlayer more particularly made from polycrystalline silicon, said layerscan be obtained by thermal oxidation of the substrate, when they areobtained by deposition and conversely can be obtained by deposition whenobtained by oxidation.

Moreover, the deposition of the oxide layer 46 in which the field oxide46a will be formed can be preceded by a thermal oxidation in order toensure a good interface with the silicon forming the substrate, as wellas layers 34 or 38.

In the same way, the etching of the different layers used in theprocesses according to the invention and carried out anisotropically,can be performed by using isotropic etching processes, such as vaporphase or liquid phase chemical etching processes, or ion machining orsputtering and vice versa. The two latter etching methods can beadvantageously used when the materials constituting the different layersare difficult to etch, which is particularly the case when theconductive layers are made from copper, silver, etc. Finally, thethickness of the different layers can be changed.

The different stages of the processes according to the invention havethe advantage of being simple to perform and are not critical. Theseprocesses consisting of a different approach from that of the generallyused integrated circuit production processes are reliable andreproducible, which has not always been the case with the prior artprocesses.

I claim:
 1. Process for the production, on a semiconductor substrate, ofan integrated circuit having reciprocally electrically insulated activecomponents in which gates of said components do not extend aboveelectrical insulations used for the reciprocal insulation of saidcomponents, said process comprising, in sequence, the followingsteps:(a) covering said semiconductor substrate with a first layer ofinsulating material in which gate insulatings will be formed, (b)depositing on the first layer of insulating material a second layerincluding a semiconductor or conductor material in which will be formedsaid gates of said active components, (c) forming a field oxide of thecircuit used for electrically insulating said active components from oneanother, (d) producing said gates of said active components in saidsecond layer, (e) producing active zones of said components by a dopingof the substrate, said doping having an opposite conductivity to that ofthe substrate, (f) forming insulating edges on the edges of said gatesof said components, (g) producing electrical contact holes of thecircuit, and (h) producing connections of the circuit.
 2. Productionprocess according to claim 1, wherein step (c) comprises the followingsuccessive steps:(1) defining the regions of said substrae in which willbe produced said active components with the aid of a first positivemask, (2) eliminating the regions of said first and second layerssurmounting the substrate, and free from said first positive mask, so asto expose regions of said substrate masked by said first positive mask,(3) preliminarily doping said semiconductor substrate in the exposedregions thereof, said preliminary doping having the same type ofconductivity as that of said semiconductor substrate and occurring priorto the doping of step (e), (4) eliminating said first positive mask, (5)depositing a third layer of an insulating material on the completestructure obtained, and (6) anisotropically etching said third layer, soas to expose the upper surface of said etched second layer locateddirectly below said third layer.
 3. Production process according toclaim 2, comprising:following step (5), on said third layer ofinsulating material, depositing a fourth layer of material obliteratingthe relief of said third layer of insulating material and performingstep (6) by simultaneously etching said third and fourth layers ofmaterials at identical etching speeds.
 4. Production process accordingto claim 3, wherein anisotropic etching of said fourth material layertakes place.
 5. Production process according to claim 2,comprising:following step (2), partially etching the substrate regionsexposed with the aid of said first positive mask.
 6. Production processaccording to claim 2, comprising performing step (2) by successivelyanisotropically etching said first and second layers of materialsurmounting said substrate.
 7. Production process according to claim 1,wherein step (b) comprises depositing a semiconductor or conductormaterial on said first layer, covering said semiconductor or conductormaterial with an insulating layer of insulating material, and depositingon said insulating layer of insulating material a temporary layer ofmaterial different from said insulating material of said insulatinglayer.
 8. Production process according to claim 7, wherein step (d)comprises the following successive steps:(1) defining the dimensions ofsaid gates of said components and electrical connections of these gatesto be produced by means of a gate negative mask, (2) eliminating theregions of said temporary layer free from said gate negative mask untilthe exposure of said insulating material layer, (3) partially etchingsaid field oxide with the aid of said gate negative mask, (4)eliminating said gate negative mask, (5) depositing on the completestructure obtained a planation/gate mask layer obliterating the reliefof said structure, (6) etching the planation/gate mask layer, so as toonly retain the material of said planation/gate mask layer in thehollowed out parts of the relief, the structure resulting from saidetching then having a planar surface, (7) eliminating the remainingtemporary layer, and (8) etching said insulating layer of insulatingmaterial and said semiconductor or conductor material until said firstlayer of insulating material is exposed, the etched planation/gate masklayer acting as a mask for said etching.
 9. Production process accordingto claim 8, comprising:between steps (4) and (5), covering the structurewith an edge insulating layer and then etching said edge insulatinglayer so as to only leave said edge insulating layer on the etched edgesof said temporary layer.
 10. Production process according to claim 8,wherein anisotropic etching of said planation/gate mask layer takesplace.
 11. Production process according to claim 7, wherein step (d)comprises the following successive steps:(1) defining the dimensions ofsaid gates of said components and electrical connections of these gatesto be produced by means of a gate negative mask, (2) eliminating theregions of said temporary layer free from said gate negative mask untilthe exposure of said insulating material layer, (3) eliminating saidgate negative mask, (4) depositing on the complete structure obtained aplanation/gate mask layer obliterating the relief of said structure, (5)etching the planation/gate mask layer, so as to only retain the materialof said planation/gate mask layer in the hollowed out parts of therelief, the structure resulting from said etching then having a planarsurface, (6) eliminating the remaining temporary layer, and (7) etchingsaid insulating layer of insulating material and said semiconductor orconductor material until said first layer of insulating material isexposed, the etched planation/gate mask layer acting as a mask for saidetching.
 12. Production process according to claim 11,comprising:between steps (3) and (4), covering the structure with anedge insulating layer and then etching said edge insulating layer so asto only leave said edge insulating layer on the etched edges of saidtemporary layer.
 13. Production process according to claim 11, whereinanisotropic etching of said planation/gate mask layer takes place. 14.Production process according to claim 1, wherein said gates of saidcomponents are produced by performing the following successive steps:(1)defining the dimensions of said gates of said components and theelectrical connections of said gates to be produced by means of a gatenegative mask, (2) using said gate negative mask, producing a firstetching of said second layer over a predetermined height, (3) partiallyetching said field oxide with the aid of said gate negative mask, (4)eliminating said gate negative mask, (5) depositing on the completestructure obtained a planation/gate mask layer of a materialobliterating the relief of said structure, (6) etching saidplanation/gate mask layer, so that all that is retained thereof are thehollowed out portions, the resulting structure then having a planarsurface, and (7) carrying out a second etching of said second layeruntil said first layer of insulating material is exposed, the etchedplanation/gate mask layer serving as a mask for said etching. 15.Production process according to claim 14, comprising:between steps (4)and (5), covering the structure with an edge insulating layer ofinsulating material, which is then etched so as to only leave said edgeinsulating layer on the etched edges of said second layer obtainedduring said first etching of said second layer.
 16. Production processaccording to claim 14, wherein definition of the dimensions of theconnections to be produced between said acitve zones of said componentstakes place during the definition of the dimensions of said gates ofsaid components by means of said gate negative mask and said field oxideis partially etched using said gate negative mask.
 17. Productionprocess according to claim 14, wherein anisotropic etching of saidplanation/gate mask layer takes place.
 18. Production process accordingto claim 1, wherein said gates of said components are produced byperforming the following successive steps:(1) defining the dimensions ofsaid gates of said components and the electrical connections of saidgates to be produced by means of a gate negative mask, (2) using saidgate negative mask, producing a first etching of said second layer overa predetermined height, (3) eliminating said gate negative mask, (4)depositing on the complete structure obtained a planation/gate masklayer of a material obliterating the relief of said structure, (5)etching said planation/gate mask layer, so that all that is retainedthereof are the hollowed out portions, the resulting structure thenhaving a planar surface, and (6) carrying out a second etching of saidsecond layer until said first layer of insulating material is exposed,the etched planation/gate mask layer serving as a mask for said etching.19. Production process according to claim 18, comprising:between steps(3) and (4), covering the structure with an edge insulating layer ofinsulating material, which is then etched so as to only leave said edgeinsulating layer on the etched edges of said second layer obtainedduring said first etching of said second layer.
 20. Production processaccording to claim 18, wherein definition of the dimensions of theconnections to be produced between said active zones of said componentstakes place during the definition of the dimensions of said gates ofsaid components by means of said gate negative mask and said field oxideis partially etched using said gate negative mask.
 21. Productionprocess according to claim 18, wherein anisotropic etching of saidplanation/gate mask layer takes place.
 22. Production process accordingto claim 1, wherein said insulating edges are formed on the edges ofsaid gates of said components by performing the following successivesteps:(1) depositing on the complete structure an insulating stripmaterial layer, (2) etching said insulating strip material layer so asto only leave said insulating strip material layer on the etched edgesof the structure, thus forming strips of said insulating strip materiallayer, (3) producing a contact holes negative mask on the structureobtained in order to define the dimensions of the electrical contacts ofsaid active zones of said components to be produced, (4) etching of saidinsulating strips not covered by said contact holes negative mask overall or part of their height, and (5) eliminating said contact holesnegative mask.
 23. Production process according to claim 22, whereindefinition of the dimensions of the connections to be produced betweensaid active zones of said components takes place during the definitionof the dimensions of the electrical contacts of said active zones ofsaid components by means of said contact holes negative mask and saidfield oxide is partially etched using said contact holes negative mark.24. Production process according to claim 22, wherein anisotropicetching of said insulating strip material layer takes place. 25.Production process according to claim 1, wherein the electricalconnections and connections of the circuit are obtained by carrying outin step (g) the following successive steps:(1) depositing on thecomplete structure at least one conductive layer of a conductivematerial in which the connections will be formed, (2) depositing on saidconductive layer a planation/contact covering layer obliterating therelief of said conductive layer, (3) etching the planation/contactcovering layer, so as to only leave it in the hollowed out portions ofsaid relief, the structure resulting from said etching then having aplanar surface, (4) eliminating the regions of the conductive layer notcovered by the etched planation/contact covering layer, and (5)eliminating the remainder of said planation/contact covering layer. 26.Production process according to claim 25, wherein two conductive layersare deposited on top of one another to form said connections. 27.Production process according to claim 25, wherein anisotropic etching ofsaid field oxide and said planation/contact covering layer takes place.28. Production process according to claim 1, wherein said second layerincludes a material selected from the group consisting ofpolycrystalline silicon, molybdenum, tantalum, titanium and tungsten.29. Production process according to claim 1, wherein said second layerincludes a material selected from the group consisting of molybdenumsilicide, tantalum silicide, titanium silicide and tungsten silicide.30. Process for the production, on a semiconductor substrate, of anintegrated circuit having active components which are electricallyinsulated from one another in which gates of said components do notextend above electrical insulations used for insulating said componentsfrom one another, comprising, in sequence, the following steps:(a)producing a field oxide of the circuit used for electrically insulatingsaid active components from one another, (b) covering said semiconductorsubstrate and said field oxide with a first layer of an insulatingmaterial in which will be formed gate insulatings, (c) depositing on thecomplete structure a second layer of a semiconductor or conductormaterial in which will be formed said gates of said active components,(d) etching said second layer of semiconductor or conductor material soas to expose said field oxide, (e) producing said gates of said activecomponents in said second layer, (f) producing active zones of saidcomponents by a doping of said semiconductor substrate, said dopinghaving an opposite conductivity to that of said semiconductor substrate,(g) producing insulating edges on the edges of said gates of thecomponents, (h) producing electrical contact holes of the circuit, and(i) producing connections of the circuit.
 31. Production processaccording to claim 30, wherein (a) comprises the following successivesteps:carrying out a preliminary doping of the whole of saidsemiconductor substrate having a conductivity of the same type as thatof said semiconductor substrate wherein said preliminary doping occursbefore the doping of step (f), depositing a field oxide layer ofinsulating material on the complete semiconductor substrate, definingthe regions of the substrate in which will be formed the activecomponents with the aid of a first negative mask, eliminating theregions of said field oxide layer of material free from said firstnegative mask, and eliminating said first negative mask.
 32. Productionprocess according to claim 30, comprising:after step (c), depositing onsaid second layer of semiconductor or conductor material a planationlayer obliterating the relief of said second layer of semiconductor orconductor material and performing step (d) by simultaneously etchingsaid second layer and said planation layer at identical etching speeds.33. Production process according to claim 32, wherein anisotropicetching of said planation layer takes place.
 34. Production processaccording to claim 30, wherein said gates of said components areproduced in step (e) by performing the following successive steps:(1)defining the dimensions of said gates of said components and theelectrical connections of said gates to be produced by means of a gatenegative mask, (2) using said gate negative mask, producing a firstetching of said second layer over a predetermined height, (3) partiallyetching said field oxide with the aid of said gate negative mask, (4)eliminating said gate negative mask, (5) depositing on the completestructure obtained a planation/gate mask layer of a materialobliterating the relief of said structure, (6) etching saidplanation/gate mask layer, so that all that is retained thereof are thehollowed out portions, the resulting structure then having a planarsurface, and (7) carrying out a second etching of said second layeruntil said first layer of insulating material is exposed, the etchedplanation/gate mask layer serving as a mask for said etching. 35.Production process according to claim 34, comprising:between steps (4)and (5), covering the structure with an edge insulating layer ofinsulating material, which is then etched so as to only leave said edgeinsulating layer on the etched edges of said second layer obtainedduring said first etching of said second layer.
 36. Production processaccording to claim 34, wherein definition of the dimensions of theconnections to be produced between said active zones of said componentstakes place during the definition of the dimensions of said gates ofsaid components by means of said gate negative mask and said field oxideis partially etched using said gate negative mask.
 37. Productionprocess according to claim 34, wherein anisotropic etching of said fieldoxide and said planation/gate mask layer takes place.
 38. Productionprocess according to claim 30, wherein said gates of said components areproduced in step (e) by performing the following successive steps:(1)defining the dimensions of said gates of said components and theelectrical connections of said gates to be produced by means of a gatenegative mask, (2) using said gate negative mask, producing a firstetching of said second layer over a predetermined height, (3)eliminating said gate negative mask, (4) depositing on the completestructure obtained a planation/gate mask layer of a materialobliterating the relief of said structure, (5) etching saidplanation/gate mask layer so that all that is retained thereof are thehollowed out portions, the resulting structure then having a planarsurface, and (6) carrying out a second etching of said second layeruntil said first layer of insulating material is exposed, the etchedplanation/gate mask layer serving as a mask for said etching. 39.Production process according to claim 38, comprising:between steps (3)and (4), covering the structure with an edge insulating layer ofinsulating material, which is then etched so as to only leave said edgeinsulating layer on the etched edges of said second layer obtainedduring said first etching of said second layer.
 40. Production processaccording to claim 38, wherein definition of the dimensions of theconnections to be produced between said active zones of said componentstakes place during the definition of the dimensions of said gates ofsaid components by means of said gate negative mask and said field oxideis partially etched using said gate negative mask.
 41. Productionprocess according to claim 38, wherein anisotropic etching of said fieldoxide and said planation/gate mask layer takes place.
 42. Productionprocess according to claim 30, wherein said insulating edges are formedon the edges of said gates of said components by performing thefollowing successive steps:(1) depositing on the complete structure aninsulating strip material layer, (2) etching said insulating stripmaterial layer so as to only leave said insulating strip material layeron the etched edges of the structure, thus forming strips of saidinsulating strip material layer, (3) producing a contact holes negativemask on the structure obtained in order to define the dimensions of theelectrical contacts of said active zones of said components to beproduced, (4) etching of said insulating strips not covered by saidcontact holes negative mask over all or part of their height, and (5)eliminating said contact holes negative mask.
 43. Production processaccording to claim 42, wherein anisotropic etching of said field oxideand said insulating strip material layer takes place.
 44. Productionprocess according to claim 42, wherein definition of the dimensions ofthe connections to be produced between said active zones of saidcomponents takes place during the definition of the dimensions of theelectrical contacts of said active zones of said components by means ofsaid contact holes negative mask and said field oxide is partiallyetched using said contact holes negative mask.
 45. Production processaccording to claim 30, wherein the electrical connections andconnections of the circuit are obtained by carrying out in step (h) thefollowing successive steps:(1) depositing on the complete structure atleast one conductive layer of a conductive material in which theconnections will be formed, (2) depositing on said conductive layer aplanation/contact covering layer obliterating the relief of saidconductive layer, (3) etching said planation/contact covering layer, soas to only leave it in the hollowed out portions of said relief, thestructure resulting from said etching then having a planar surface, (4)eliminating the regions of said conductive layer not covered by theetched planation/contact covering layer, (5) eliminating the remainderof said planation/contact covering layer.
 46. Production processaccording to claim 45, wherein two conductive layers are deposited ontop of one another to form said connections.
 47. Production processaccording to claim 45, wherein anisotropic etching of said field oxideand said planation/contact covering layer takes place.
 48. Productionprocess according to claim 30, wherein said second layer includes amaterial selected from the group consisting of polycrystalline silicon,molybdenum, tantalum, titanium and tungsten.
 49. Production processaccording to claim 30, wherein said second layer includes a materialselected from the group consisting of molybdenum silicide, tantalumsilicide, titanium silicide and tungsten silicide.